The Design of the Microarchitecture of UltraSPARC TM-1 - Proceedings of the IEEE

The realization of a high pe@ormance modem microprocessor involves hundreds of person-years of conception, logic design, circuit design, layout drawing, etc. In order to leverage effectively the 5-10 millions of transistors available, careful microarchitecture tradeoff analysis must be pe@ormed. This paper describes not only the microarchitecture of UltraSPARC-I, a 167 MHz 64-b fourway superscalar processor, but more importantly it presents the analysis and tradeoffs that were made “en route” to the$nal chip. Among several issues, the in-order execution model is compared with alternatives, variations of the issue-width of the machine as well as the number of functional units are described, subtle features that are part of the memory hierarchy are explained, and the advantages of the packet-switched interconnect are exposed.